The present disclosure relates to integrated circuit structures and methods, and more specifically, to methods that produce devices that have active area shapes that reduce device size.
Transistorized devices continue to enjoy size reductions because of technological advances. For example, gate all around (GAA) device structures are replacing fin-type field effect transistors (FINFET) in order to achieve continued scaling, which may otherwise be limited by poor electrostatics in FINFET devices.
However, conventional static random access memory (SRAM) architectures may not scale with GAA devices (such as nanosheet FET or vertical FET (VFET) devices) and hence, SRAM scaling may be challenged beyond FINFET technology. For example, it can be difficult to scale the bitcell area of SRAM structures due to various contact and isolation requirements. As a result, new constructs are being presented to allow continued scaling in SRAM with GAA structures like VFET.